| C 语言 |
https://www.runoob.com/cprogramming/c-tutorial.html |
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| 1.2 Verilog 简介 |
http://www.runoob.com/w3cnote/verilog-intro.html |
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| 1.3 Verilog 环境搭建 |
http://www.runoob.com/w3cnote/verilog-install.html |
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| 1.4 Verilog 设计方法 |
http://www.runoob.com/w3cnote/verilog-design-method.html |
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| 2.1 Verilog 基础语法 |
http://www.runoob.com/w3cnote/verilog-basic-syntax.html |
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| 2.2 Verilog 数值表示 |
http://www.runoob.com/w3cnote/verilog-number.html |
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| 2.3 Verilog 数据类型 |
http://www.runoob.com/w3cnote/verilog-data-type.html |
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| 2.4 Verilog 表达式 |
http://www.runoob.com/w3cnote/verilog-expression.html |
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| 2.5 Verilog 编译指令 |
http://www.runoob.com/w3cnote/verilog-compile-instruction.html |
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| 3.1 Verilog 连续赋值 |
http://www.runoob.com/w3cnote/verilog-assign.html |
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| 3.2 Verilog 时延 |
http://www.runoob.com/w3cnote/verilog-time-delay.html |
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| 4.1 Verilog 过程结构 |
http://www.runoob.com/w3cnote/verilog-process-structure.html |
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| 4.2 Verilog 过程赋值 |
http://www.runoob.com/w3cnote/verilog-process-assign.html |
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| 4.3 Verilog 时序控制 |
http://www.runoob.com/w3cnote/verilog-timing-control.html |
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| 4.4 Verilog 语句块 |
http://www.runoob.com/w3cnote/verilog-statements-block.html |
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| 4.5 Verilog 条件语句 |
http://www.runoob.com/w3cnote/verilog-condition-statement.html |
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| 4.6 Verilog 多路分支语句 |
http://www.runoob.com/w3cnote/verilog-case.html |
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| 4.7 Verilog 循环语句 |
http://www.runoob.com/w3cnote/verilog-loop.html |
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| 4.8 Verilog 过程连续赋值 |
http://www.runoob.com/w3cnote/verilog-deassign.html |
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| 5.1 Verilog 模块与端口 |
http://www.runoob.com/w3cnote/verilog-module-port.html |
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| 5.2 Verilog 模块例化 |
http://www.runoob.com/w3cnote/verilog-generate.html |
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| 5.3 Verilog 带参数例化 |
http://www.runoob.com/w3cnote/verilog-defparam.html |
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| 6.1 Verilog 函数 |
http://www.runoob.com/w3cnote/verilog-function.html |
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| 6.2 Verilog 任务 |
http://www.runoob.com/w3cnote/verilog-task.html |
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| 6.3 Verilog 状态机 |
http://www.runoob.com/w3cnote/verilog-fsm.html |
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| 6.4 Verilog 竞争与冒险 |
http://www.runoob.com/w3cnote/verilog-competition-hazard.html |
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| 6.5 Verilog 避免 Latch |
http://www.runoob.com/w3cnote/verilog-latch.html |
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| 6.6 Verilog 仿真激励 |
http://www.runoob.com/w3cnote/verilog-testbench.html |
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| 6.7 Verilog 流水线 |
http://www.runoob.com/w3cnote/verilog-pipeline-design.html |
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| 7.1 Verilog 除法器设计 |
http://www.runoob.com/w3cnote/verilog-dividend.html |
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| 7.2 Verilog 并行 FIR 滤波器设计 |
http://www.runoob.com/w3cnote/verilog-fir.html |
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| 7.3 Verilog 串行 FIR 滤波器设计 |
http://www.runoob.com/w3cnote/verilog-serial-fir.html |
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| 7.4 Verilog CIC 滤波器设计 |
http://www.runoob.com/w3cnote/verilog-cic.html |
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| 7.5 Verilog FFT 设计 |
http://www.runoob.com/w3cnote/verilog-fft.html |
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| 7.6 Verilog DDS 设计 |
http://www.runoob.com/w3cnote/verilog-dds.html |
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| 8.1 Verilog 数值转换 |
http://www.runoob.com/w3cnote/verilog-numerical-conversion.html |
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| 常见网络类型 |
http://www.runoob.com/ml/ml-common-network-types.html |
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| 深度学习vs传统机器学习 |
http://www.runoob.com/ml/ml-deep-learning-traditional-machine-learning.html |
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| 前向传播与反向传播 |
http://www.runoob.com/ml/ml-forward-and-backward-propagation.html |
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| 神经网络的基本结构 |
http://www.runoob.com/ml/ml-structure-of-neural-networks.html |
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| 深度强化学习 |
http://www.runoob.com/ml/ml-deep-reinforcement-learning.html |
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| 强化学习 Q-learning 与 SARSA |
http://www.runoob.com/ml/ml-qlearning-sarsa.html |
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| 强化学习探索vs开采 |
http://www.runoob.com/ml/ml-exploration-exploitation.html |
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| runoob.com |
www.runoob.com/ |
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